Static memory cells in certain environments such as communication satellite orbital space are, or will likely be particularly susceptible to soft errors or single event upsets (SEUs). See E. G. Gussehower, K. A. Lynch and D. H. Brenteger, "DMPS Dosimetry Data: A Space Measurement and Mapping of Upset Causing Phenomena," IEEE Trans. Nuclear Science NS-34, pp. 1251-1255 (1987) and H. T. Weaver, et al., "An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM," IEEE Trans. Nuclear Science, NS-34, pp. 1281-1286 (1987). A soft error or single event upset (SEU) typically is caused by electron-hole pairs created by, and along the path of a single energetic particle as it passes through an integrated circuit, such as a memory. Should the energetic particle generate the critical charge in the critical volume of a memory cell, then the logic state of the memory is upset. This critical charge, by definition, is the minimum amount of electrical charge required to change the logic state of the memory cell. The critical charge may also enter the memory through direct ionization from cosmic rays. See T. C. May and M. H. Woods, "Alpha Particle Induce Soft Errors in Dynamic Memories," IEEE Trans. Electronic Devices, ED-26, p. 2 (1979) and J. C. Pickel, J. T. Blaudfood, Jr., "CMOS RAM Cosmic Ray-Induce Error Rate Analysis," IEEE Trans. on Nuclear Science, Vol. NS-28, pp. 3962-3967 (1981). Alternatively, the critical charge may result from alpha particles (helium nuclei). One example of SEU can be seen in FIG. 1 which illustrates a cross-sectional view of a CMOS inverter. When alpha particle p strikes bulk semiconductor material in p-channel MOS transistor Pch, it generates electron-hole pairs as shown by the respective minus and plus marks. Assuming that the n-channel transistor Nch is on and that p-channel transistor P-ch is off, the holes (indicated by plus signs) which collect (see arrows toward drain D) at drain D can change the voltage at output OUT from a logic low to a logic high. The electrons as indicated by the minus signs will diffuse toward circuit supply voltage Vcc. A charge generating particle hit on transistor Nch has the opposite effect with positive charge drifting towards ground and negative charges collecting at output OUT, thus possibly changing the logic state of the inverter.
A memory cell which provides hardening against SEU was described in application Ser. No. 241,681, filed Sept. 7, 1988. A schematic drawing of this cell is illustrated in FIG. 2. Memory cell 2 is constructed according to well known methods of cross-coupled inverter realization and thus CMOS inverters are used in memory cell 2. A first CMOS inverter 4 in memory cell 2 is made up of p-channel transistor 6 and n-channel transistor 8 having their source-to-drain paths connected in series between Vdd and ground, and having their gates tied together. The second CMOS inverter 5 in memory cell 2 is similarly constructed, with p-channel transistor 10 and n-channel transistor 12 having their source-to-drain paths connected in series between Vcc and ground and their gates also common. The cross-coupling is accomplished by the gates of transistors 6 and 8 being connected to the drains of transistors 10 and 12 being connected to the drains of transistors 10 and 12 (node S1 of FIG. 1b), and by the gates of transistors 10 and 12 being connected to the drains of transistors 6 and 8 (node S2 of FIG. 1b). The above described arrangement and structure of inverter 4 coupled to inverter 5 are commonly referred to as cross-coupled inverters, while the lines connecting gates and drains are each referred to as a cross-coupling line. N-channel transistor 14 has its source-to-drain path connected between node S2 and a first bit line BL, and has its gate connected to word line WL. N-channel pass transistor 16 similarly has its source-to-drain path connected between node S1 and a second bit line BL.sub.--, and has its gate also connected to word line WL. Pass transistors 14, 16 when enabled, allow data to pass into and out of memory cell 2 from bit lines BL and BL.sub.-- respectively. Bit lines BL and BL.sub.-- carry data into and out of memory cell 2. Pass transistors 14, 16 are enabled by word line WL which is a function of the row address in an SRAM. The row address is decoded by a row decoder in the SRAM such that one out of n word lines is enabled, where n is the number of rows of memory cells in the memory which is a function of memory density and architecture. P-channel transistors 22 and 24 are connected across an associated cross-coupling line joining the input of one inverter to the output of another inverter. Additionally, the gate of transistor 22 is common with that of transistor 6 and the gate of transistor 24 is common with that of transistor 10. This circuit can be built on a thin film which lies on an insulator such as is done in silicon on insulator technology (SOI).
In operation, the voltages of nodes S1 and S2 will necessarily be logical complements of one another, due to the cross-coupled nature of CMOS inverters 4, 5 within memory cell 2. When word line WL is energized by the row decoder (not shown), according to the row address received at address inputs to an address buffer (not shown) connected to the row decoder, pass transistors 14, 16 will be turned on, coupling nodes S1 and S2 to bit lines BL.sub.-- and BL respectively. Accordingly, when word line WL is high, the state of memory cell 2 can establish a differential voltage on BL and BL.sub.--. Alternatively, peripheral circuitry forcing a voltage on BL and BL.sub.-- can alter the state of memory cell 2. The sizes of the transistors shown in FIG. 1 are generally chosen such that when pass transistors 14, 16 are turned on by word line WL; a differentially low voltage at bit line BL with respect to bit line BL.sub.-- can force node S2 to a logic low level; and a differentially low voltage at bit line BL.sub.-- with respect to bit line BL can force node S1 to a logic low level. However, the sizes of the transistors shown in FIG. 2 are also chosen such that when transistors 14 and 16 are on; a differentially high voltage at bit line BL with respect to bit line BL.sub.-- will not force node S2 high; nor will a differentially high voltage at bit line BL.sub.-- with respect to bit line BL force node S1 high. Therefore writing into memory cell 2 is accomplished by pulling the desired bit line and thus the desired side of cell 2 at either node S1 or node S2 low, which in turn due to feedback paths in cell 2, causes the opposite side of cell 2 to have a logic high state.
SEU protection is provided by the circuit shown in FIG. 2 in that transistors 22 and 24 provide additional delay in the feedback paths so as to allow recovery of the memory cell from a energetic particle hit. The gate capacitances of transistors 22 and 24 provide SEU protection both by increasing the feedback delay and by decreasing the voltage change incurred by collection of a given amount of charge. However, the layout for the cell shown in FIG. 2 does not necessarily optimize the amount of capacitance achieved which is capable of being produced within the given cell size. For instance, in certain situations even more SEU hardening may be required than possible within the memory cell of FIG. 2 within a given cell size.